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VHDL Programming for FPGA

MYR4000


Date: Subject to availability of trainer and participants (2 days)
Time: 9:30AM – 5:30PM

20% discount for group registration (min 3 pax), please click here to arrangement payment.

 

INTRODUCTION

VHDL is a hardware programming language popularly used to design and program in hardware such as Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuits (ASIC).

VHDL is a structured language for logic design.

 

COURSE OBJECTIVES

This training is an important course to have a jumpstart in Very Large Scale Integration Technology (VLSI) and will combine lectures and lab sessions to provide a good background on the language and the digital design flow in general.

 

TOPICS

First, an introduction to the history of VHDL will be provided.

Then, the training will cover in detail the syntax, structure, and constructs of the language. In addition, it will introduce related concepts such as VLSI design flow in general, digital design concepts such as combinational and sequential circuits, behavioral and dataflow modelling, delays, finite state machine (Mealy and Moore) modelling, hierarchical design and coding guidelines and verification.

Finally, it will introduce how to write a good testbench.

The training will also utilise industry-based tools, ModelSim and Quartus II to perform the design entry, synthesis, and simulation.

There will be hands-on lab exercises to develop VHDL code for common digital systems, compile the code, solve errors and understand warnings, view the schematic after synthesis, run simulations to verify the functionality/timing and program the VHDL code on hardware (optional).

This course will be able to support the Altera and Xilinx FPGA development boards.

 

 

LEARNING OUTCOME

The knowledge gained can be applied on any digital design by employing either a bottom-up or top-down design.

    1. Familiarize and grasp VHDL syntax
    2. Understand the different VHDL coding styles
    3. Write synthesizable VHDL code
    4. Write simple testbenches
    5. Simulate the VHDL code
    6. Synthesize the VHDL code

 

TARGET AUDIENCE

The course is suitable for Engineering undergraduates, IC designers, digital logic designers, design engineers, verification engineers and VHDL programmers from both the industry and academia.

This training is offered at the beginner level, intermediate level and advanced level.

Basic background knowledge on digital electronics and digital circuit design will enhance the understanding of the VHDL concepts.

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