Verilog Programming for FPGA
Date: Subject to availability of trainer and participants (2 days)
Time: 9:30AM – 5:30PM
20% discount for group registration (min 3 pax), please click here to arrangement payment.
Verilog is a hardware programming language popularly used to design and program in hardware such as Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuits (ASIC).
Verilog is a structured language for logic design.
This training is an important course to have a jumpstart in Very Large Scale Integration Technology (VLSI) and will combine lectures and lab sessions to provide a good background on the language and the digital design flow in general.
First, an introduction to the history of Verilog will be provided.
Then, the training will cover in detail the syntax, structure, and constructs of the language.
In addition, it will introduce related concepts such as VLSI design flow in general, digital design concepts such as combinational and sequential circuits, behavioral and dataflow modelling, delays, finite state machine (Mealy and Moore) modelling, hierarchical design and coding guidelines and verification.
Finally, it will introduce how to write a good testbench.
The training will also utilise industry-based tools, ModelSim and Quartus II to perform the design entry, synthesis, and simulation.
There will be hands-on lab exercises to develop Verilog code for common digital systems, compile the code, solve errors and understand warnings, view the schematic after synthesis, run simulations to verify the functionality/timing and program the Verilog code on hardware (optional).
This course will be able to support the Altera and Xilinx FPGA development boards.
The knowledge gained can be applied on any digital design by employing either a bottom-up or top-down design.
- Familiarize and grasp Verilog syntax
- Understand the different Verilog coding styles
- Write synthesizable Verilog code
- Write simple testbenches
- Simulate the Verilog code
- Synthesize the Verilog code
The course is suitable for Engineering undergraduates, IC designers, digital logic designers, design engineers, verification engineers and Verilog programmers from both the industry and academia.
This training is offered at the beginner level, intermediate level, and advanced level.
Basic background knowledge on digital electronics and digital circuit design will enhance the understanding of the Verilog concepts.
Associate Professor Dr. Florence Choong graduated with a Bachelor of Engineering (Honours) majoring in Electronics (First class) in 2002, Masters of Engineering Science (MEngSc) degree majoring in VLSI in 2005, PhD in Engineering majoring in VLSI in 2012 and Masters in Business Administration (MBA) from the University of Derby, UK. in 2014.
She is also a Chartered Engineer with IET (UK) and a Fellow (FHEA) with Advanced HE. She is a certified trainer under the Pembangunan Sumber Manusia Berhad (Ministry of Human Resource, Malaysia).
Being passionate in the area of research, training and education, she now has a total of more than 15 years’ experience in various reputable higher education institutions and training/consultancy work for industries such as Intel Corporation, Mini Circuits Technologies, Emerald Systems, Panasonic and many more.
She has also collaborated with local companies such as DreamCatcher Consulting and Multimedia Development Corporation (MDEC) to run several training programmes.
She is author and co-author of numerous international journal and conference papers in VLSI system design and digital system. She has also supervised undergraduate and post graduate students to completion.
- Ph.D (Electronic Engineering),
- MEngSc (Electronic Engineering),
- MBA (UK), BEng (Hons) Electronics,
- Fellow (FHEA),
- Certified Trainer (HRDF)